Further, this technology (MTL or I.sup.2 L) and its various applications has been described in a number of U.S. Patents and Publications, a number of which are identified below:
U.S. Pat. No. 3,643,231 entitled "Monolithic Associative Memory Cell" granted Feb. 15, 1972 to F. H. Lohrey and S. K. Wiedmann, and of common assignee herewith. The Lohrey et al patent discloses an associative memory storage cell having two cross-connected transistors with the word line for the cell connected to the common emitters of the two transistors and having each of the bases of the two transistors connected to the base of an input/output transistor. The emitter of each of these input/output transistors is connected to a separate bit line and the collectors of the input/output transistors are connected together and to the associative sense amplifier. To associatively search the memory, one of the bit lines is lowered. This causes the input/output transistor connected to the lowered bit line to conduct and thereby give a no-match signal to the associative sense amplifier if its base is connected to the base of the conducting one of the two cross-connected transistors and it causes that transistor to remain nonconductive and thereby give a match signal to the associative sense amplifier if it is connected to the base of the non-conducting one of the two cross-connected transistors.
U.S. Pat. No. 3,736,477 entitled "Monolithic Semiconductor Circuit Concept of High Packing Density" granted May 29, 1973 to H. H. Berger and S. K. Wiedmann and of common assignee herewith. The Berger et al patent discloses a monolithic semiconductor circuit comprising a lateral PNP transistor and an inversely operated vertical NPN transistor. The lateral transistor is formed by a pair of mutually spaced P-type regions diffused in an N-type semiconductor body. The collector region has diffused therein a region of N-type and constituting the collector of the vertical transistor. The semiconductor body constitutes the base region of the lateral transistor and the emitter region of the vertical transistor.
U.S. Pat. No. 3,815,106 entitled "Flip-Flop Memory Cell Arrangement" granted June 4, 1974 to S. K. Wiedmann, and of common assignee herewith. The Wiedmann patent discloses a memory cell arrangement which allows the powering of only two row cells at any one time. This results in lower power dissipation in the cells and also permits the driving circuits to operate at a much lower power level, thereby further reducing the power dissipation per chip.
U.S. Pat. No. 3,816,758 entitled "Digital Logic Circuit" granted June 11, 1974 to H. H. Berger and S. K. Wiedmann, and of common assignee herewith. The Berger et al patent discloses a digital logic circuit comprising a first transistor of a predetermined conductivity type and having an emitter, a base and a collector, a second transistor of the opposite conductivity type and having an emitter, a base and a collector, an input adapted to receive a digital logic signal, an output, a current source, means connecting said first transistor emitter to said current source, means connecting said first transistor base to said second transistor emitter, means connecting said first transistor collector and said second transistor base to said input, and means connecting said second transistor collector to said output.
U.S. Pat. No. 3,866,531 entitled "Schottky Loaded Emitter Coupled Memory Cell For Random Access Memory" granted May 27, 1975 to J. L. McNeill. The McNeill patent discloses a memory cell for a random access memory, the cell including a bistable circuit having first and second cross-coupled transistors with plural emitters. One emitter of each of the first and second transistors is coupled in common. The collector loads for the first and second transistors are provided by respective Schottky diodes which enable the differential voltage in the memory cell to remain low and the cell to be unsaturated over an order of magnitude of current increase to provide for a higher ratio of cell read current to cell store current. Additionally, hard saturation of the memory cell which would otherwise increase the write time is eliminated by this construction.
U.S. Pat. No. 3,993,918 entitled "Integrated Circuits" granted Nov. 23, 1976 to A. W. Sinclair. The Sinclair patent discloses a master/slave bistable arrangement which operates on current levels rather than voltage levels and with a single input of clock pulses. There are different bias current levels which are advantageously supplied by multilayer current injection structures in integrated form.
U.S. Pat. No. 4,021,786 entitled "Memory Cell Circuit and Semiconductor Structure Therefore" granted May 3, 1977 to H. W. Peterson. The Peterson patent discloses a memory cell which comprises a word line, a pair of bit lines, a pair of current sources each having a first side coupled to a corresponding one of the bit lines; and a bistable circuit means operatively coupled to the word line and to another side of each of the current sources, whereby the bistable circuit means assumes one stable state upon the application of a voltage on one bit line, and assumes another stable state upon the application of a voltage on the other bit line.
U.S. Pat. No. 4,090,255 entitled "Circuit Arrangement For Operating A Semiconductor Memory System"granted May 16, 1978 to H. H. Berger et al., and of common assignee herewith. The Berger et al patent discloses a circuit arrangement for operating the read/write cycles of an integrated semiconductor memory storaage system whose storage cells consist of flip flops with bipolar switching transistors, Schottky diodes as read/write elements coupling the cell to the bit lines, and high-resistivity resistors, or transistors controlled as current sources, as load elements, in several phases. This is accomplished through coupling the storage cell to both read/write circuits and restore/recovery circuits via the bit lines and by selective pulsing of the cell with the read/write circuits and the restore/recovery circuits. This permits high speed, low operating current, large scale memory systems to be built.
U.S. Pat. No. 4,158,237 (GE 9-77-016) entitled "Monolithically Integrated Storage Cells" granted June 12, 1979 to S. K. Wiedmann and of common assignee herewith. The Wiedmann patent discloses a monolithically integrated storage cell which includes a flip-flop circuit with two cross-coupled, bipolar switching transistors and one load element each connected by means of one terminal to the collectors of the switching transistors, the storage cell being controlled via a word line connected to the other terminal of both load elements and via one bit line each of a bit line pair connected to the emitter of each switching transistor.
U.S. Pat. No. 4,021,786 entitled "Memory Cell Circuit and Semiconductor Structure Therefore" granted May 3, 1977 to H. W. Peterson. The ABSTRACT of the Peterson patent reads as follows: "A new and improved memory cell is provided which comprises a word line, a pair of bit lines, a pair of current sources each having a first side coupled to a corresponding one of the bit lines, and a bistable circuit means operatively coupled to the word line and to another side of each of the current sources, whereby the bistable circuit means assumes one stable state upon the application of a voltage on one bit line, and assumes another stable state upon the application of a voltage on the other bit line. In addition, several embodiments of semiconductor structures are proveded for the new and improved memory cell".
Reference is made to United Kingdom patent application No. 8700/77 (GE 9-76-005) filed Mar. 2, 1977, publication No. 1,569,800, published June 18, 1980.
IBM Technical Disclosure Bulletin publication entitled "I.sup.2 L/MTL Storage Cell Layout" by H. H. Berger et al., Vol. 22, No. 10, Mar. 1980, pages 4604-4605.
IBM Technical Disclosure Bulletin publication (GE 8-77-0015) entitled "MTL Storage Cell" by S. K. Wiedmann, Vol. 21, No. 1, June 1978, pages 231-232.
"Merged-Transistor Logic (MTL)--A Low-Cost Bipolar Logic Concept" by Horst H. Berger and Siegfried K. Wiedmann, IEEE Journal of Solid-State Circuits, Vol. SC-7, No. 5, Oct. 1972, pages 341-346.
"Integrated Injection Logic: A New Approach to LSI" by Kees Hart and Arie Slob, IEEE Journal of Solid-State Circuits, Vol SC-7, No. 5, Oct. 1972, pages 346-351.
"I.sup.2 L Takes Bipolar Integration A Significant Step Forward" by R. L. Horton et al., Electronics, Feb. 6, 1975, pages 83-90.
"I.sup.2 L Puts It All Together For 10-bit a-d Converter Chip" by Paul Brokaw, Electronics/Apr. 13, 1978, pages 99-105.
"Integrated Injection Logic Shaping Up As Strong Bipolar Challenge to MOS", Electronic Design 6, Mar. 15, 1974, pages 28 and 30.
The invention concerns a monolithically integrated storage arrangement with storage cells arranged in a matrix, which comprise two I.sup.2 L structures each made up of an injector and an associated inverting switching transistor and connected in the form of a flip-flop by a cross-coupling between the collector of one and the base of the other switching transistor, the operating current and the read/write currents of the storage cells of a matrix column being applied via a bit line pair connected to the injectors of said storage cells, and the selection of the storage cells of a matrix line being effected via a common address line coupled to the emitters of the switching transistors of said storage cells.
The field of logical circuits with bipolar transistors has been marked by considerable progress in recent years, which has attracted the attention of the experts and which under the term MTL (Merged Transistor Logic) or I.sup.2 L (Integrated Injection Logic) has been referred to extensively in technical literature. Attention is drawn, for example, to the articles in the IEEE Journal of Solid-State Circuits, Vol. SC-7, No. 5, Oct. 1972, pp. 340 ff and 346 ff. Relevant patents are, for example, U.S. Pat. Nos. 3,736,477 and 3,816,758. This injection logic concept is essentially based on inverting single- or multiple-collector transistors which are fed close to (order of magnitude of one diffusion length) their emitter-base junctions by the injection of minority charge carriers inside the semiconductor body.
A basic structure of this logic concept, as described in the aforementioned U.S. patents, is made up in such a manner that zones of the second conductivity type, which serve as emitter and collector zones of a lateral transistor structure, are arranged spaced from each other in a semiconductor layer of a first conductivity type and that the collector zone of the lateral transistor structure includes at least one further zone of a conductivity type opposite thereto, which serves as a collector zone of an inversely operated vertical, complementary transistor structure. The collector zone of the lateral transistor structure simultaneously forms the base zone of the vertical transistor structure. The base zone of the lateral and the emitter zone of the inversely operated vertical transistor structure are formed by the semiconductor layer of the first conductivity type. For operating this semiconductor structure as a logical basic circuit, a current is impressed into the emitter zone of the lateral transistor structure, which as a function of the input signal applied to the collector zone of the lateral and the base zone of the vertical transistor, respectively, controls the current supplying the inverted output signal through the vertical transistor structure. By merging the zones of the same doping and connected to the same potential, a structure of optimum integration is obtained, the manufacture of which requires only two diffusion processes in the embodiment described.
Other known examples of this basic circuit include a layer structure with four zones of different conductivity types, which comprise two vertical, monolithically merged transistor structures and which are suitably operated. In this case, minority charge carriers are also injected via the emitter zone of one transistor, which causes current to be supplied to the basic circuit, while the output signal is supplied via the other transistor structure.
The inverting, logical basic circuits described are most suitable for the design of logical circuits and are equally suitable as componenets for monolithically integrated storage cells. Such storage cells are used in particular in digital data processing systems. The storage cells are arranged in a matrix, so that via corresponding selection means each cell can be addressed, while data are written into or read from it.
It is known that inverting logical circuits require two stages to obtain storage cells in the manner of bistable multivibrators and flip-flops, respectively. Thus, a storage cell includes two such basic circuits which are symmetrically designed and whereby the output of one circuit is connected to the input of the other to provide a feedback condition. In this manner, the necessary cross-coupling, as exists in the usual flip-flops, is obtained.
From German OS 2 307 739 [(FI 9-71-084) - U.S. Pat. No. 3,815,106] a storage cell is known which includes two of the logical basic circuits described and in which the collector of the inverting transistor of one basic circuit is in each case connected to the base of the inverting transistor of the other basic circuit. The two inverting transistors are inversely operated, forming the actual flip-flop transistors. The complementary transistors of the two basic circuits, via which the injection of minority charge carriers and thus the power supply is effected and which are connected via a separate line, serve as load elements for both flip-flop transistors. For the purpose of addressing, that means for writing and reading a storage cell, the base of each flip-flop transistor is additionally connected to the emitter of an associated additional addressing transistor which is also complementary and whose collector is connected to the associated bit line, and whose base is connected to the address line. In addition to the injecting transistor forming the load element, a further addressing transistor is necessary which is also formed by a lateral transistor structure.
Proceeding from the known inverting logical basic circuit, German OS 2 612 666 [(GE 9-76-005) United Kingdom Patent Application No. 8700/77 filed Mar. 2, 1977 and published as Publication No. 1 569 800 on June 18, 1980] concerns an improved basic circuit which particularly, because of its operation offers considerable advantages in connection with logical circuits and which by means of sense circuits largely reduces the load imposed on the actual signal path. This is accomplished by sensing the conductive state of the inverting transistor of the basic "Integrated Injection Logic" (I.sup.2 L) circuit with the aid of a sense circuit incorporated in the injection current circuit and thus in the operating current circuit. This sensing is effected as a function of the current reinjected into the injection zone with a conductive inverting transistor. When this principle, as is also described in the afore-mentioned Offenlegungsschrift, is used in a circuit including two such circuits connected in the form of a flip-flop to serve as a storage cell, both the supply of the operating current and the coupling of the read/write signals are effected via bit lines connected to the injection zone. In this manner no separate addressing transistors are required, and the additional injection zone necessary for the known storage cell is eliminated.
Certain problems may be encountered with the I.sup.2 L basic circuit described in the afore-mentioned Offenlegungsschrift and the storage cell produced with its aid, if importance is attached to minimum dimensions for the structure and thus to maximum integration density. These minimum dimensions, i.e., the minimum area requirements obtainable for an I.sup.2 L basic circuit, are, for technological reasons, essentially a function of the minimum dimensions obtainable for the contact and diffusion windows in the photolithographic processes used during manufacture.
An I.sup.2 L structure manufactured in accordance with the ground rules determined by the technology applied and aimed at minimum area requirements is characterized in that the facing injecting and reinjecting edges of the lateral transistor are of the shortest possible length. This edge length determines the efficiency of the injection and reinjection of the minority charge carriers. In other words, this edge length determines the current amplification of the lateral transistor in the forward and the backward direction.
When the I.sup.2 L basic circuit is used in storage cells designed in the manner of a flip-flop, these current amplifications may be too low to obtain reliably operating storage arrangements.
This becomes apparent from the fact that during the sensing of the conductive state of the inverting transistor the signal supplied on the injection zone, as a result of charge carriers being reinjected by the conductive transistor, may be too weak to provide a clearly defined read signal.